1. Field of the Invention
The invention relates generally to a flash memory device and a method of erasing the same, and more particularly to, a flash memory device and a method of erasing the same, which can improve the erase speed and characteristic of the flash memory device.
2. Description of the Prior Art
In semiconductor nonvolatile memory devices such as EEPROM (electrically erasable and programmable read only memory) and flash memory devices, NOR type semiconductor nonvolatile memory devices (hereinafter called ‘flash memory device’) in which a program operation wherein electrons are injected into a floating gate by means of a channel hot carrier electron (hereinafter called ‘CHE’) injection method is performed and an erase operation using a Fowler-Nordheim (hereinafter called ‘F-N’) tunneling phenomenon is performed, have been widely used.
Generally, the entire data program procedure in this flash memory device includes program, erase, recovery and read operations as shown in Table 1 below.
TABLE 1Gate VoltageDrain VoltageSource VoltageBulk Voltage(VG)(VD)(VS)(VB)Program    9 V  5 V0 V0 VErase−7.5 VFloatingFloating9 VRecovery    0 V  5 V0 V0 VRead    4 V0.8 V0 V0 V
As can be seen from Table 1, the program operation is performed using the CHE injection method. In this operation, the gate voltage (VG) of a voltage that is relatively higher than the drain voltage (VD) and the source voltage (VS) is applied to the control gate, so that electrons are injected into the floating gate.
The erase operation is performed using the F-N tunneling phenomenon. In this operation, the gate voltage (VG) of a low voltage is applied to the control gate, so that the electrons injected into the floating gate are drawn. This erase operation consists of pre-program, erase, and recovery (or post-program) operations (hereinafter called ‘post-program’). At this time, the pre-program operation is selectively performed.
The pre-program and post-program operations are performed in order to raise the threshold voltage (Vt) of the memory cell that is relatively low to a desired threshold voltage before and after the erase operation. Generally, in the operations, an iterative program and verify method wherein program and verify operations are sequentially repeatedly performed has been widely used.
In the iterative program and verify method, pre-program, pre-program verify, erase, erase verily, post-program and post-program verify operations are sequentially performed. This will be below described by reference to the flowchart for explaining the method of erasing the flash memory device shown in FIG. 1.
Referring to FIG. 1, the operation of erasing the flash memory device includes the pre-program step (first step), the erase step (second step) and the post-program step (third step), as described above.
In the first step (pre-program step), the pre-program operation is performed (S101), wherein a pre-program bias voltage is set according to an erase start command and the set bias voltage is then supplied to corresponding memory cells to be pre-programmed for an allocated time. After the pre-program operation is completed through the step (S110), a pre-program verify operation is performed (S102), wherein a pre-program verify bias voltage is set and the set bias voltage is then supplied to the corresponding memory cells to be programmed, in order to check whether the pre-program operation was normally performed. If the pre-program verify operation was not normally performed in the step (S102), the process returns to the step (S101) wherein the steps (S101˜S103) are iteratively performed, and if the pre-program verify operation was normally performed in the step (S102), the process moves to a step (S104) wherein the erase operation is performed (S103).
In the second step (erase step), the erase operation is performed (S104), wherein an erase bias voltage is set and the set bias voltage is then supplied to corresponding memory cells to be erased for an allocated time. After the erase operation is finished through the step (S104), an erase verify operation is performed (S105), wherein an erase verify bias voltage is set and the set bias voltage is then supplied to the corresponding memory cells to be erased, in order to check whether the erase operation was normally performed. If the erase operation was not normally performed in the step (S105), the process returns to the step (S104) wherein the steps (S104˜S106) are iteratively performed, and if the erase operation was normally performed in the step (S105), the process moves to a step (S107) wherein the post-program operation is performed (S106).
In the third step (post-program step), the post-program operation is performed (S107), wherein a post-program bias voltage is set and the set bias voltage is then supplied to corresponding memory cells to be post-programmed for an allocated time. After the post-program operation is finished through the step (S107), a post-program verify operation is performed (S108), wherein a post-program verify bias voltage is set and the set bias voltage is then supplied to the corresponding memory cells to be post-programmed, in order to check whether the post-program operation was normally performed. If the post-program verify operation was not normally performed in the step (S108), the process returns to the step (S107) wherein the steps (S107˜S109) are iteratively performed, and if the post-program verify operation was normally performed in the step (S108), the post-program step is finished (S19).
The conventional erase operation mentioned above has the following several problems.
First, as the bias voltages applied upon the program (or erase) and verify operations that are iteratively performed in each of the steps (first step˜third step) are different in the erase operation, it is required that operations for setting the bias voltages corresponding to the respective steps (first step˜third step) be iteratively performed. Due to this, the operation time for setting the bias voltage is accumulated during the entire erase operation. In particular, time consumed in the pre-program and post-program steps is almost same to time consumed in an actual erase step due to accumulated operating time for setting the bias voltage, thus increasing the erase time.
Second, in the conventional erase operation, time taken to apply the bias voltages in the respective steps (first step˜third step) is fixed to the allocated time (e.g. specific time). The bias voltages are continuously applied to the corresponding memory cells during remaining time even though the corresponding memory cells are controlled to the threshold voltages during the allocated time. Due to this, as the threshold voltages of the corresponding memory cells exceed the desired threshold voltages, distribution of the erase memory cells widens. Thus, there are problems such as over erase and reduction in the sensing margin in the memory cell.
Third, in the conventional erase operation, the pre-program and post-program operations of the actual program and erase operations are performed using a normal program algorithm (e.g. a sequential process wherein upon the program and verify operations, the process moves to next 8 bits when the verify operation is passed by iteratively applying the bias voltage), regardless of sector erase or chip erase, or the erase operation of one sector or entire sectors is performed wherein the read operation is intact applied to the pre-program or the post-program, and the pre-program, the post-program and the verify operation are then iteratively performed 8 bits or 16 bits unit being the program and read unit in a code flash memory. Therefore, in case of the chip erase, the erase time same to the sum of time taken to erase the respective sectors is consumed.
Fourth, in the conventional erase operation, the iterative program and verify method wherein the program and verify operations are iteratively performed must be used. Thus, a relatively complicated state machine circuit is needed. Due to this, it is difficult to add various functions including a multi-tasking function to the complicated state machine circuit.